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fifo程序
- 用verilog语言在fpga中实现fifo功能！-using Verilog language in which they simply realize fifo function!
异步FIFO存储器的控制设计
- 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
source_code
- verilog code fifo memory usb
FIFO
- FIFO的VERILOG代码编写 可综合的Verilog FIFO存储器-The VERILOG code FIFO write comprehensive Verilog FIFO memory
fifo
- verilog实现fifo，ise中仿真，chipscope调试-verilog achieve fifo, ise in the simulation, chipscope debugging
fifo
- fifo designed by haneesh (me) in verilog-fifo designed by haneesh (me) in verilog
fifo
- Verilog HDL实现复杂逻辑设计FIFO-Verilog HDL to achieve FIFO
FIFO
- FIFO is accomplished with the code which is written using the language of verilog.FIFO is the means of first output while first input
FIFO
- 将ROM的正弦波数据输入FIFO存储器，然后输出，有modelsim仿真波形-Verilog FIFO ROM mif sine
Verilog FIFO
- FPGA的FIFO源代码，经过调试，下载即可用。适合模块调用或嵌入，也适合初学者学习。
FIFO
- sample verilog FIFO design
FIFO_ASY
- 异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
FIFO
- 用verilog语言的实现FIFO存储器，以先进先出的方式处理数据(The FIFO memory is implemented in Verilog language, and data is processed in FIFO)
fifo
- fifo in qurtuas using verilog
FIFO
- FIFO code in verilog
异步FIFO
- 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
FIFO
- FPGA片内FIFO实例，对FPGA片内FIFO进行读写测试(FPGA FIFO example, reading and writing FIFO in FPGA chip.)
fifo
- Verilog HDL实现通用的FIFO的一个demo，可以参考这个程序根据自己的需求更改深度和宽度，以及标志位(Verilog HDL implements a demo of a generic FIFO that you can refer to to to change the depth and width, as well as the flag bits, depending on your needs)
verilog实例 [43项]
- 一些采用verilog描述的数字功能模块，有常见的同步异步FIFO，RAM等模块，适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
异步FIFO
- 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)